1. Field of the Invention
The present invention relates to improving signal quality in a digital signaling system, such as a computer system memory.
2. Background of the Related Art
Digital signaling systems used in computers employ a driver for generating a digital signal and a receiver for receiving the digital signal. For example, a computer memory system may include a processor including a driver to generate an I/O (input/output) signal, and a memory module including a receiver. The signal generated by a digital signaling system is a time-dependent voltage signal used to represent different logic levels, such as a logical “0” and “1.” At the receiver, the voltage of the signal may be compared with a reference voltage (Vref) to determine which logic state is being represented at each instance of a clock signal. Some amount of noise is typically present in the channel, which affects the signal voltage. Therefore, it is desirable to maximize the voltage margin between the signal and the reference voltage. A fixed Vref value is typically set during an initial training phase.
As computer technology advances, processor speeds continue to increase, creating a demand for faster memory systems capable of keeping pace with the increasing processor speeds. Faster memory bus speeds are facilitated, in part, by reducing the voltages of I/O data signals, to avoid excessive transition time from one signal level to another (e.g. from a logical “0” to “1”). However, reducing the signal voltage also reduces the voltage margin between the signal voltage and the Vref with which the signal is compared to identify a logical value. If the magnitude of the fixed reference voltage is not suitable, then the available voltage margin may be inadequate and result in reduced signal reliability.